1. Technical Field
The invention relates to MOS transistors. More specifically, the invention relates to the improvement of drive-strength and leakage of deep submicron MOS transistors.
2. Discussion of the Prior Art
Users of conventional complementary metal-oxide semiconductor (CMOS) technology currently face some difficult choices as the minimum feature size of such devices shrinks to below 100 nanometers and power supply voltage is reduced to less than 1.0V. A typical layout of a 0.18 micron transistor 100 is shown in FIG. 1. The transistor is manufactured over a well 110 where a diffusion area 120 is created. The gate 130 of the transistor 100 is formed over a well 120, and has a width w, for example, of 0.18 micron as a minimum width for a transistor that is fabricated using 0.18 micron technology. Contacts 140 and 141 comprise one terminal of the NMOS transistor, for example the drain, and the contact 150 provides another terminal of the transistor 100, for example the source. A contact 131 is connected to the gate 130. There are other minimal feature sizes, such as a minimal size for the well x and a minimum distance from the edge of the well to the diffusion area 120 marked as y. Dimensions, such as w, x and y are generally process dependent. Power supply voltage is reduced in correspondence with the minimum feature size to maintain a limit on the electrical field across the oxide, which is made thinner as feature size is decreased. Therefore, power supply voltage is decreased from 3.3V for 0.35-micron CMOS technology to 1.8V for 0.18 micron technology, and is further expected to be at the 1.0V level for 100 nanometers CMOS technology.
While power supply voltage is decreased, the threshold voltage of NMOS transistors has stayed between 0.45V and 0.35V. The relationship between the NMOS threshold voltage Vth and CMOS power supply VDD is known to be very critical. The threshold voltage determines the leakage current Ioff of the transistor when it is in its OFF state. As the threshold voltage is driven lower, the leakage current increases.
The drain current of the transistor is a direct function of the overdrive of the transistors, measured as the difference between power supply VDD and threshold voltage Vth. The drain current of the transistor determines the time required to charge the load capacitance from ground to the level of power supply VDD, or vice versa. This overdrive voltage has decreased constantly as the power supply decreased from 3.3V to 1.0V, while threshold voltage decreased only from 0.45V to 0.35V. For 0.1 micron technology, the threshold voltage of the transistors is scaled below 0.35V at the expense of a very high OFF stage leakage current IOFF, which ranges between 1 nA to 100 nA for a transistor having a width of 1 miron. For a transistor with gate width of 10 microns, the OFF current increases to ten times the value stated above, i.e. from 10 nA to 1000 nA. For CMOS technology having a 0.1-micron minimum feature size, a typical VLSI chip is expected to contain over 100 million gates. Given a leakage of every gate of 1 microamperes, this results in a whopping 100 amperes of leakage current.
A scheme for dynamically controlling the transistor threshold voltage has been proposed by Takamiya et al. in High Performance Electrically Induced Body Dynamic Threshold SOI MOSFET (EIB-DTMOS) with Large Body Effect and Low Threshold Voltage IEDM Technical Digest 1998. Takimiya et al. suggest a scheme that shorts the gate and the substrate of the transistors, thereby causing the substrate voltage of the transistor to increase as the gate voltage is increased for an n-channel MOS (NMOS) transistor. This scheme is proposed for NMOS transistors fabricated on silicon-on-insulator (SOI) substrates, where the transistor substrate is totally isolated. This scheme manipulates the threshold voltage by changing the bias of the substrate or well in the positive direction for a NMOS transistor, along with a positive signal at the gate. As the substrate or well-to-source voltage becomes positive, the depletion layer width is reduced resulting in lower threshold voltage for the transistor, thereby increasing the current from the transistor. In the native form, Takimiya et al. is applicable only for circuits using a power supply voltage of less than 0.6V because this scheme turns on the substrate-to-source diode and the leakage from this diode must be limited or one would trade one type of leakage for another, i.e. from drain-to-source leakage to substrate-to-source leakage. Another approach is discussed in U.S. Pat. No. 6,521,948 by Ebina trying to solve is the accumulation of holes, created by impact ionization, in the floating body region of a semiconductor-on-insulator (SOI) transistor. The accumulated holes cause a relatively uncontrolled decrease in threshold voltage. Therefore, Ebina places the body into a slight, presumably controlled, forward bias conditions with respect to the source by connecting a reverse biased diode. Specifically, Ebina concentrates on controlling the current in the ON state, in particular to avoid its variable and uncontrolled increase. The use of a backward biased diode is deficient in several ways. Firstly, the reverse current through the diode varies over orders of magnitude and is highly sensitive to temperature. Secondly, the expanded polysilicon gate region creates a depletion region in the SOI substrate, and more explicitly in fully depleted SOI, which effectively cuts off the end of the gate from the source or the drain region during the ON state of the transistor. Secondly, while Ebina deals effectively with voltage ranges of 2 volts and above, it fails to provide a solution for transistor operating in lower voltages as common in modern designs.
Douseki in U.S. Pat. No. 5,821,769 describes a method for the control of the threshold voltage of an MOS transistor by connecting a MOS transistor between the gate and the substrate to control the threshold voltage. Douseki requires the addition of another transistor for every transistor whose threshold voltage is dynamically controlled. The adjusted threshold voltage is fixed by the power supply voltage and the threshold voltage of the additional transistor. The area penalty is fairly large for this approach and it requires additional process steps.
There is a therefore a need in the art for a technology which can reduce the leakage of MOS transistors without adversely affecting the drive current or the drain current under saturation conditions, which are defined as drain-source voltage and gate-source voltage equal to the power supply voltage (VDS=VGS=VDD). It would be further advantageous if the solution addressed low voltage operation in the range of 2V and below.